mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.1 overview 1.1.1 overview the mn101e series of 8-bit single-chip microcompute rs (the memory expansion version of mn101c series) incorporate multiple types of peripheral functions. this chip series is well suited for camera, tv, cd, printer, tele- phone, home appliance, ppc, fax machine, music instrument and other applications. this lsi brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim- ple efficient instruction set. mn101ef93g have an internal 128 kb of rom and 6 kb of ram. peripheral func- tions include 5 external interrupts, in cluding nmi, 9 timer counters, 4 types of serial interfaces, a/d converter, watchdog timer and buzzer output. the system configura tion is suitable for system control microcontroller. with 3 oscillation systems (internal frequency: 16 mhz, high-speed crystal/ceramic frequency: max. 10 mhz, low-speed crystal/ceramic freq uency: 32.768 khz) contained on the chip, the system clock can be switched to high-speed frequency input (normal mode) or pll inpu t (pll mode), or low-sp eed frequency input (slow mode). the system clock is generated by dividing the osc illation clock or pll clock. the best operation clock for the system can be selected by switching its frequency ratio by programming. high speed mode has normal mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and pll), by 2 (fpll/2), and the double speed mode which is based on the clock not dividing fpll. a machine cycle (minimum instruction execution time) in normal mode is 200 ns when the original oscillation fosc is 10 mhz (pll is not used). a machine cycle in the double speed mode, in which the cpu operates on the same clock as the external clock, is 100 ns when fosc is 10 mhz. a machine cycle in the pll mode is 50 ns (max- imum). 1.1.2 product summary this manual describes the following model. table:1.1.1 product summary model rom size ram size classification package mn101ef93g 128 kb 6 kb flash eeprom version 80 pin lqfp
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.2 hardware functions ? feature - memory capacity: rom 128 kb ram 6 kb - package: 80-pin lqfp (14 mm ? 14 mm / 0.65 mm pitch, halogen free) panasonic "halogen free" semiconductor products re fer to the products made of molding resin and interposer which conform to the following standards. - bromine : 900 ppm (maximum concentration value) - chlorine : 900 ppm (maximum concentration value) - bromine + chlorine : 1500 ppm (maximum concentration value) the above-mentioned standards are based on the numerical value described in iec61249-2-21. antimony and its compounds are not added intentionally. - machine cycle: high-speed mode 0.05 ? s / 20 mhz (4.0 v to 5.5 v) low-speed mode 62.5 ? s / 32 khz (4.0 v to 5.5 v) - oscillation circuit: 3 channel oscillation circuit internal oscillation (frc): 16 mhz crystal/ceramic (fosc): maximum 10 mhz crystal/ceramic (fx): maximum 32.768 khz -clock multiplication circuit (pll circuit) pll circuit output clock (fpll): fosc multiplied by 2, 3, 4, 5, 6, 8, 10, 1/2 ? frc multiplication by 4, 5 enable -clock gear for system clock system clock (fs): fpll divided by 1, 2, 4, 16, 32, 64, 128 -clock gear for control clock of peripheral function control clock of peripheral function (fpll-div): stop or fpll divided by 1, 2, 4, 8, 16 - memory bank: expands data memory space by the ba nk system (by 64 kb, 16 banks) source address bank / destination address bank - operation mode: normal mode (high-speed mode) slow mode (low-speed mode) halt mode stop mode (the operation clock can be switched in each mode.)
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e - operating voltage: 4.0 v to 5.5 v - operation ambient temperature: -40 ? c to +85 ? c - interrupt: 25 levels - non-maskable interrupt and watchdog timer overflow interrupt - timer 0 interrupt - timer 1 interrupt - timer 2 interrupt - timer 3 interrupt - timer 6 interrupt - time base timer interrupt - timer 7 interrupt - timer 7 compare register 2 match interrupt - timer 8 interrupt - timer 8 compare register 2 match interrupt - serial interface 0 interrupt - serial interface 0 ua rt reception interrupt - serial interface 1 interrupt - serial interface 1 ua rt reception interrupt - serial interface 2 interrupt - serial interface 2 ua rt reception interrupt - serial interface 4 interrupt - serial interface 4 stop condition interrupt - a/d conversion interrupt - irq0: edge selectable, nois e filter connection available - irq1: edge selectable, nois e filter connection available - irq2: edge selectable, noise filter c onnection available, both edges interrupt - irq3: edge selectable, noise filter c onnection available, both edges interrupt - irq4: edge selectable, noise f ilter connection available, both edges interrupt, key scan interrupt - timer counter: 9 timers - 8-bit timer for general use ? 4 sets - 16-bit timer for general use ? 2 sets - 8-bit free-run timer ? 1 set - time base timer ? 1 set - baud rate timer ? 1 set timer 0 (8-bit timer for general use) - square wave output (timer pulse output) - added pulse (2-bit) type pwm output can be output to large current pin tm0ioa - event count - simple pulse measurement
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e - clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fx, external clock, timer a output timer 1 (8-bit timer for general use) - square wave output (timer pulse output) can be output to large current pin tm1ioa - event count - 16-bit cascade connected (with timer 0) - clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fx, external clock, timer a output timer 2 (8-bit timer for general use) - square wave output (timer pulse output) - added pulse (2-bit) type pwm output can be output to large current pin tm2ioa - event count - simple pulse measurement - 24-bit cascade connected (with timer 0 and timer 1) - clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fp ll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fx, external clock, timer a output timer 3 (8-bit timer for general use) - square wave output (timer pulse output) can be output to large current pin tm3ioa - event count - 16-bit cascade connected (with timer 2) - 32-bit cascade connected (with timer 0 and timer 1 and timer 2) - clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/ 32, fpll-div/128, fs/2, fs/4, fs/8, fx, external clock, timer a output timer 6 (8-bit free-run timer, time base timer) 8-bit free-run timer - clock source fpll-div, fpll-div/2 12 , fpll-div/2 13 , fs, fx, fx/2 2 , fx/2 3 , fx/2 12 , fx/2 13 time base timer - interrupt generation cycle fpll-div/2 7 , fpll-div/2 8 , fpll-div/2 9 , fpll-div/2 10 , fpll-div/2 13 , fpll-div/2 15 , fx/2 7 , fx/2 8 , fx/2 9 , fx/2 10 , fx/2 13 , fx/2 15 timer 7 (16-bit timer for general use) - square wave output (timer pulse output) - high precision pwm output (cycle/duty continuous changeable) can be output to large current pin tm7ioa - event count - input capture function (both edges can be operated) - clock source fpll-div, fpll-div/2, fpll-div/4, fp ll-div/16, fs, fs/2, fs/4, fs/16, timer a divided by 1, 2, 4, 16, external clock divided by 1, 2, 4, 16 timer 8 (16-bit timer for general use) - square wave output (timer pulse output) - high precision pwm output (cycle/duty continuous changeable) can be output to large current pin
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e tm8ioa - event count - input capture function (both edges can be operated) - clock source fpll-div, fpll-div/2, fpll-div/4, fp ll-div/16, fs, fs/2, fs/4, fs/16, timer a divided by 1, 2, 4, 16, external clock divided by 1, 2, 4, 16 timer a (baud rate timer) - clock output for peripheral functions - clock source fpll-div, fpll-div/2, fpll-div/4, fpll-div/8, fpll-div/16, fpll-div/32, fs/2, fs/4 - watchdog timer time-out cycle can be selected from fs/2 16 , fs/2 18 , fs/2 20 on detection of 2 errors, forc ibly hard reset inside lsi. operation start timing is selectable. (a t reset release or write to register) - buzzer output/ reverse buzzer output output frequency can be selected from fpll-div/2 9 , fpll-div/2 10 , fpll-div/2 11 , fpll-div/2 12 , fpll-div/2 13 , fpll-div/2 14 , fx/2 3 , fx/2 4 - a/d converter: 10-bit ? 12 channels - serial interface: 4 channels serial 0: uart (full duplex)/ clock synchronous clock synchronous serial interface - transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, timer 0 to 3 or timer a divided by 1, 2, 4, 8, 16, external clock - msb/lsb can be selected as th e first bit to be transferred, arbitrary sizes of 2 to 8 bits are selectable. - sequence transmission, recep tion or both are available full duplex uart - baud rate timer, selected from timer 0 to 3 or timer a - parity check, overrun erro r/ framing error detection - transfer size 7 to 8 bits can be selected serial 1: uart (full duplex)/ clock synchronous clock synchronous serial interface - transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, timer 0 to 3 or timer a divided by 1, 2, 4, 8, 16, external clock - msb/lsb can be selected as th e first bit to be transferred, arbitrary sizes of 2 to 8 bits are selectable. - sequence transmission, recep tion or both are available. full duplex uart - baud rate timer, selected from timer 0 to 3 or timer a - parity check, overrun erro r/ framing error detection - transfer size 7 to 8 bits can be selected serial 2: uart (full duplex)/ clock synchronous clock synchronous serial interface - transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, timer 0 to 3 or timer a divided by 1, 2, 4, 8, 16, external clock - msb/lsb can be selected as th e first bit to be transferred,
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e arbitrary sizes of 2 to 8 bits are selectable. - sequence transmission, recep tion or both are available. full duplex uart - baud rate timer, selected from timer 0 to 3 or timer a - parity check, overrun erro r/ framing error detection - transfer size 7 to 8 bits can be selected serial 4: multi master iic/ clock synchronous clock synchronous serial interface - transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/32, fs/2, fs/4, timer 0 to 3 or timer a divided by 1, 2, 4, 8, 16, external clock - msb/lsb can be selected as th e first bit to be transferred, arbitrary sizes of 2 to 8 bits are selectable. - sequence transmission, recep tion or both are available. multi master iic - 7-bit slave address is settable. - general call communication mode is supported. - automatic reset: power detection level: 4.3 v (at rising), 4.2 v (at falling) - led driver: 8 pins (port a) - ports i/o ports 72 pins serial interface pins 21 pins timer i/o 11 pins buzzer output pins 2 pins a/d input pins 12 pins external interrupt pins 5 pins led (large current) driver 8 pins high-speed oscillation 2 pins low-speed oscillation 2 pins special pins 8 pins operation mode input pins 3 pins reset input pin 1 pin analog reference voltage input pin 1 pin power pins 3 pins
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.3 pin description 1.3.1 pin configuration figure:1.3.1 pin configuration (80-pin lqfp) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 led0/tm0ioa/an0/pa0 160p73 led1/tm1ioa/an1/pa1 259p72/sbt2 led2/tm2ioa/an2/pa2 358p71/sbi2/rxd2 led3/tm3ioa/an3/pa3 4 57 p70/sbo2/txd2 led4/an4/pa4 5 56 p67/sbt4a/scl4a led5/tm7ioa/an5/pa5 6 55 p66/sbo4a/sda4a led6/tm8ioa/an6/pa6 754p65/sbi4a led7/an7/pa7 853p64 vref+ 952p63/tm3ioa mmod 10 51 p62/tm1iob atrst 11 50 p61 nrst/p27 12 49 p50/sbo0a/txd0a/key0 xi/p90 13 48 p51/sbi0a/rxd0a/key1 xo/p91 14 47 p52/SBT0A/key2 vss 15 46 p53/buzzer/key3 osc1/p25 16 45 p54/nbuzzer/key4 osc2/p26 17 44 p55/key5 vdd5 18 43 p56/key6 vdd18 19 42 p57/key7 dmod 20 41 p47 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p77/sbt1b p76/sbi1b/rxd1b p75/sbo1b/txd1b p74 p83 p82 p81 p80 p87 p86 p85 p84 p95 p94 p93 p92 pb0/an8 pb1/an9 pb2/an10 pb3/an11 sbt0b/p45 p46 irq3/p23 irq4/p24 p10 sbo4b/sda4b/p33 sbo0b/txd0b/p43 sbi0b/rxd0b/p44 sbt4b/scl4b/p34 sbi4b/p35 tm7iob/sbi1a/rxd1a/p00 irq1/p21 irq2/p22 p04 p05 p06 t m8iob/sbo1a/txd1a/p01 sbt1a/p02 tm0iob/tm2iob/p03 irq0/p20 mn101ef93g 80pin lqfp
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.3.2 pin specification pins special functions i/o direction control pin control functions description p00 tm7iob in/out p0dir0 p0plu0 timer 7 input/output sbi1a in/out serial 1 data input rxd1a in/out uart 1 data input p01 tm8iob in/out p0dir1 p0plu1 timer 8 input/output sbo1a in/out serial 1 data input/output txd1a in/out uart 1 data input/output ocd_data in/out on-boad programmer data pin p02 sbt1a in/out p0dir2 p0plu2 serial 1 clock input/output ocd_clk in/out on-boad programmer clock supply pin p03 tm0iob in/out p0dir3 p0plu3 timer 0 input/output tm2iob in/out timer 2 input/output p04 - in/out p0dir4 p0plu4 - p05 - in/out p0dir5 p0plu5 - p06 - in/out p0dir6 p0plu6 - p10 - in/out p0dir10 p0plu10 - p20 irq0 in/out p2dir0 p2plu0 external interrupt 0 p21 irq1 in/out p2dir1 p2plu1 external interrupt 1 p22 irq2 in/out p2dir2 p2plu2 external interrupt 2 p23 irq3 in/out p2dir3 p2plu3 external interrupt3 p24 irq4 in/out p2dir4 p2plu4 external interrupt4 p25 osc1 in/out p2dir5 p2plu5 ceramic/crystal high-speed clock input p26 osc2 in/out p2dir6 p2plu6 ceramic/crystal high-speed clock output p27 nrst in/out - - reset p33 sb04b in/out p3dir3 p3plu3 serial 4 data input/output sda4b in/out multi-master iic 4 data input/output p34 sbt4b in/out p3dir4 p3plu4 serial 4 clock input/output scl4b in/out multi-master iic 4 clock input/output p35 sbi4b in/out p3dir5 p3plu5 serial 4 data input p43 sbo0b in/out p4dir3 p4plu3 serial 0 data input/output txd0b in/out uart 0 data input/output p44 sbi0b in/out p4dir4 p4plu4 serial 0 data input rxd0b in/out uart 0 data input p45 sbt0b in/out p4dir5 p4plu5 serial 0 clock input/output p46 - in/out p4dir6 p4plu6 - p47 - in/out p4dir7 p4plu7 - p50 key0 in/out p5dir0 p5plu0 key interrupt 0 sbo0a in/out serial 0 data input/output txd0a in/out uart 0 data input/output p51 key1 in/out p5dir1 p5plu1 key interrupt 1 sbi0a in/out serial 0 data input rxd0a in/out uart 0 data input
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e p52 key2 in/out p5dir2 p5plu2 key interrupt 2 SBT0A in/out serial 0 clock input/output p53 key3 in/out p5dir3 p5plu3 key interrupt 3 buzzer in/out buzzer output p54 key4 in/out p5dir4 p5plu4 key interrupt 4 nbuzzer in/out buzzer reverse output p55 key5 in/out p5dir5 p5plu5 key interrupt 5 p56 key6 in/out p5dir6 p5plu6 key interrupt 6 p57 key7 in/out p5dir7 p5plu7 key interrupt 7 p61 - in/out p6dir1 p6plu1 - p62 tm1iob in/out p6dir2 p6plu2 timer 1 input/output p63 tm3iob in/out p6dir3 p6plu3 timer 3 input/output p64 - in/out p6dir4 p6plu4 - p65 sbi4a in/out p6dir5 p6plu5 serial 4 data input p66 sbo4a in/out p6dir6 p6plu6 serial 4 data input/output sda4a in/out multi-master iic 4 data input/output p67 sbt4a in/out p6dir7 p6plu7 serial 4 clock input/output scl4a in/out multi-master iic 4 clock input/output p70 sbo2 in/out p7dir0 p7plu0 serial 2 data input/output txd2 in/out uart 2 data input/output p71 sbi2 in/out p7dir1 p7plu1 serial 2 data input rxd2 in/out uart 2 data input p72 sbt2 in/out p7dir2 p7plu2 serial 2 clock input/output p73 - in/out p7dir3 p7plu3 - p74 - in/out p7dir4 p7plu4 - p75 sbo1b in/out p7dir5 p7plu5 serial 1 data input/output txd1b in/out uart 1 data input/output p76 sbi1b in/out p7dir6 p7plu6 serial 1 data input rxd1b in/out uart 1 data input p77 sbt1b in/out p7dir7 p7plu7 serial 1 clock input/output p80 - in/out p8dir0 p8plu0 - p81 - in/out p8dir1 p8plu1 - p82 - in/out p8dir2 p8plu2 - p83 - in/out p8dir3 p8plu3 - p84 - in/out p8dir4 p8plu4 - p85 - in/out p8dir5 p8plu5 - p86 - in/out p8dir6 p8plu6 - p87 - in/out p8dir7 p8plu7 - p90 xi in/out p9dir0 p9plu0 ceramic/crystal low-speed clock input p91 xo in/out p9dir1 p9plu1 ceramic/crystal low-speed clock output p92 - in/out p9dir2 p9plu2 - p93 - in/out p9dir3 p9plu3 - p94 - in/out p9dir4 p9plu4 - p95 - in/out p9dir5 p9plu5 - pins special functions i/o direction control pin control functions description
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e pa0 an0 in/out padir0 paplu0 analog 0 input led0 in/out led driving pin 0 tm0ioa in/out timer 0 input/output pa1 an1 in/out padir1 paplu1 analog 1 input led1 in/out led driving pin 1 tm1ioa in/out timer 1 input/output pa2 an2 in/out padir2 paplu2 analog 2 input led2 in/out led driving pin 2 tm2ioa in/out timer 2 input/output pa3 an3 in/out padir3 paplu3 analog 3 input led3 in/out led driving pin 3 tm3ioa in/out timer 3 input/output pa4 an4 in/out padir4 paplu4 analog 4 input led4 in/out led driving pin 4 pa5 an5 in/out padir5 paplu5 analog 5 input led5 in/out led driving pin 5 tm7ioa in/out timer 7 input/output pa6 an6 in/out padir6 paplu6 analog 6 input led6 in/out led driving pin 6 tm8ioa in/out timer 8 input/output pa7 an7 in/out padir7 paplu7 analog 7 input led7 in/out led driving pin 7 pb0 an8 in/out pbdir0 pbplu0 analog 8 input pb1 an9 in/out pbdir1 pbplu1 analog 9 input pb2 an10 in/out pbdir2 pbplu2 analog 10 input pb3 an11 in/out pbdir3 pbplu3 analog 11 input pins special functions i/o direction control pin control functions description
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.3.3 pin functions pins no i/o function description vdd5 18 - power connect pins apply 4.0 v to 5.5 v to vdd5 and 0 v connect 0.1 ? f + 1 ? f or larger bypass capacitor for internal power stabilization. vss 15 - vdd18 19 - internal power output pin this pin is output 1.8 v from in ternal power circuit. don?t use the power supply to external device. for internal power circuit output stability, connect at least 0.1 ? f + 1 ? f one bypass capacitor between vdd18 and vss. osc1 16 input high speed operation clock input pin connect thes e oscillation pins to cerami c or crystal ocsillators for high-frequency clock operation. if the clock is an external input, connect it to osc1 and leave osc2 open. the chip will not oper- ate with an external clock when using stop mode. osc2 17 output high speed operation clock output pin nrst 12 i/o reset pin [active low] this pin resets the chip when power is turned on, is allocated as p27 and contains an internal pull-up resistor (typ. 50 k ? ). setting this pin low initialize the internal state of the device. thereafter, setting the input to high releases the reset. the hardware waits for the system clock to stabilize, then processes the reset interrupt. if a capacitor is to be inserted between nrst and vss, it is recom- mended that a discharge diode be placed between nrst and vdd5. atrst 11 input auto reset setting pin input "high" to enable auto reset function and "low? to disable this function p00 21 i/o i/o port 0 7-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p0dir register. a pull-up resistor for each bit can be selected individually by p0plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p01 22 p02 23 p03 24 p04 25 p05 26 p06 27 p10 33 i/o i/o port 1 1-bit cmos tri-state i/o port. it can be set as either an input or out- put by p1dir register. a pull-up resistor can be selected by p1plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p20 28 i/o i/o port 2 7-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p2dir register. a pull-up resistor for each bit can be selected individually by p2plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance) p21 29 p22 30 p23 31 p24 32 p25 16 p26 17 p27 12 input input port 2 p27 has an n-channel open-drain configuration. p33 34 i/o i/o port 3 3-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p3dir register. a pull-up resistor for each bit can be selected individually by p3plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p34 35 p35 36 p43 37 i/o i/o port 4 5-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p4dir register. a pull-up resistor for each bit can be selected individually by p4plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p44 38 p45 39 p46 40 p47 41
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e p50 49 i/o i/o port 5 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p5dir register. a pull-up resistor for each bit can be selected individually by p5plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p51 48 p52 47 p53 46 p54 45 p55 44 p56 43 p57 42 p61 50 i/o i/o port 6 7-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p6dir register. a pull-up resistor for each bit can be selected individually by p6plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p62 51 p63 52 p64 53 p65 54 p66 55 p67 56 p70 57 i/o i/o port 7 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p7dir register. a pull-up resistor for each bit can be selected individually by p7plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p71 58 p72 59 p73 60 p74 61 p75 62 p76 63 p77 64 p80 65 i/o i/o port 8 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p8dir register. a pull-up resistor for each bit can be selected individually by p8plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p81 66 p82 67 p83 68 p84 69 p85 70 p86 71 p87 72 p90 13 i/o i/o port 9 6-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by p9dir register. a pull-up resistor for each bit can be selected individually by p9plu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). p91 14 p92 73 p93 74 p94 75 p95 76 pa0 1 i/o i/o port a 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by padir register. a pull-up resistor for each bit can be selected individually by paplu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). pa1 2 pa2 3 pa3 4 pa4 5 pa5 6 pa6 7 pa7 8 pins no i/o function description
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e pb0 80 i/o i/o port b 4-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by pbdir register. a pull-up resistor for each bit can be selected individually by pbplu register. at reset, the input mode is selected and pull-up resistor is disabled (high impedance). pb1 79 pb2 78 pb3 77 sbo0a 49 output serial interface transmission data out- put pins transmission data output pins for serial interface 0,1,2,4. the out- put configuration, either coms push-pull or nch open-drain can be selected in p0odc, p3odc, p4odc, p5odc, p6odc and p7odc registers. pull-up resistor can be selected in p0plu, p3plu, p4plu, p5plu, p6plu, and p7plu registers. select out- put mode in p0dir, p3dir, p4dir, p5dir, p6dir, and p7dir registers and set serial data output mode in serial mode register 1 (sc0md1, sc1md1, sc2md1, sc4md1). these can be used as normal i/o pins when serial interface is not used. sbo0b 37 sbo1a 22 sbo1b 62 sbo2 57 sbo4a 55 sbo4b 34 sbi0a 48 input serial interface reception data input pins reception data input pins for serial interface 0,1,2,4. pull-up resis- tor can be selected in p0plu, p3plu, p4plu, p5plu, p6plu and p7plu registers. select the output mode in p0dir, p3dir, p4dir, p5dir, p6dir and p7dir registers and select serial data input mode in serial mode register 1 (sc0md1, sc1md1, sc2md1, sc4md1). these can be used as normal i/o pins when serial interface is not used. sbi0b 38 sbi1a 21 sbi1b 63 sbi2 58 sbi4a 54 sbi4b 36 SBT0A 47 i/o serial interface clock i/o pins clock i/o pins for serial interface 0,1,2,4. the output configuration, either coms push-pull or nch open-drain can be selected in p0odc, p3odc, p4odc, p5odc, p6odc and p7odc registers. pull-up resistor can be selected in p0plu, p3plu, p4plu, p5plu, p6plu and p7plu registers. select clock i/o in p0dir, p3dir, p4dir, p5dir, p6dir and p7dir registers and serial mode register 1 (sc0md1, sc1md1, sc2md1, sc4md1) with the communication mode. these can be used as normal i/o pins when serial interface is not used. sbt0b 39 sbt1a 23 sbt1b 64 sbt2 59 sbt4a 56 sbt4b 35 txd0a 49 output uart transmission data output pins in serial interface 0,1,2 in uart mode, this pin is configured as the transmission data output pin. the output configuration, either coms push-pull or nch open-drain can be selected in p0odc, p4odc, p5odc, p6odc and p7odc registers. pull-up resistor can be selected by p0plu, p4plu, p5plu(d), p6plu and p7plu registers. select the ou tput mode in p0dir, p4dir, p5dir, p6dir and p7dir registers and select serial data output mode in serial mode register 1 (sc0md1, sc1md1, sc2md1). these can be used as normal i/o pins when serial interface is not used. txd0b 37 txd1a 22 txd1b 62 txd2 57 rxd0a 48 input uart reception data output pins in serial interface 0,1,2 in uart mode, this pin is configured as the reception data input pin. pull-up resistor can be selected in p0plu, p4plu, p5plu(d), p6plu and p7plu registers. select the input mode in p0dir, p4dir, p5dir, p6dir and p7dir registers and select serial input in serial mode register 1 (sc0md1, sc1md1, sc2md1). these can be used as normal i/o pins when serial interface is not used. rxd0b 38 rxd1a 21 rxd1b 63 rxd2 58 sda4a 55 i/o iic data i/o pins in serial interface 4 in iic mode, this pin is configured as the data i/ o pin. for the output configurat ion, select nch open-drain in p3odc and p6odc register and set pull-up resistor in p3plu and p6plu register. select the output mode in p0dir register and p6dir register select serial data i/o mode by serial mode register 1 (sc4md1). these can be used as normal i/o pin when serial interface is not used. sda4b 34 scl4a 56 i/o iic clock i/o pins in serial interface 4 in iic mode, this pin is configured as the clock i/o pin. for the output configuration, select nch open-drain in p0odc and p6odc register and set pull-up resistor by p0plu and p6plu register. select the output mode at p0dir register and p6dir register select serial clock i/o mode in serial mode register 1 (sc4md1). these can be used as normal i/o pin when serial interface is not used scl4b 35 pins no i/o function description
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e tm0ioa 1 i/o timer i/o pins event counter clock input pin, timer output and pwm signal output pin for 8-bit timer 0 to 3. to use this pin as event clock input, con- figure it as input by p0dir, p6di r and padir register. in the input mode, pull-up resistor can be selected in p0plu, p6plu, and paplu registers. for timer output, pwm signal output, select the special function pin in p0omd1, p0omd2, p6omd and paomd registers, and set to the output mode in p0dir, p6dir and padir registers. these can be used as normal i/o pins when timer i/o pin is not used. tm0iob 24 tm1ioa 2 tm1iob 51 tm2ioa 3 tm2iob 24 tm3ioa 4 tm3iob 52 buzzer 46 output buzzer output pins piezoelectric buzzer driving pin. buzzer output is available to port 5. the driving frequency can be set in dlyctr register. in order to select buzzer output, select the special function pin in p5omd reg- ister, and set p5dir register to the output mode. at the same time, select buzzer output in oscillation stabilization wait control register (dlyctr). these can be used as normal i/o pins when buzzer output is not used. nbuzzer 45 tm7ioa 6 i/o timer i/o pins event counter clock input pin, timer output and pwm signal output pin for 16-bit timer7and 8. to use this pin as event clock input, con- figure it as input with p0dir and padir registers. in the input mode, pull-up resistor can be selected by p0plu and paplu reg- isters. for timer output, pwm signal output, select the special function pin in p0omd1 and paomd registers, and set to the out- put mode in p0dir and padir registers. these can be used as normal i/o pins when not used as timer i/o pins. tm7iob 21 tm8ioa 7 tm8iob 22 vref+ 9 - a/d reference voltage input pin reference power supply pin for a/d converter. normally, the val- ues of v ref+ = v dd5 is used. an0 1 input analog input pins analog input pins for 12-channel, 10-bit a/d converter. select the analog input by paimd, pbimd register. when not used for analog input, these pins can be used as normal input pins. an1 2 an2 3 an3 4 an4 5 an5 6 an6 7 an7 8 an8 80 an9 79 an10 78 an11 77 irq0 28 input external interrupt external interrupt input pins. select the external interrupt input enable by irqcnt register. the valid edge for irq0 to 4 can be selected with irqnicr register. irq2 to 4 can be set at both edges at pin voltage level. when not used for interrupts, these can be used as normal input pins. irq1 29 irq2 30 irq3 31 irq4 32 key0 49 input key interrupt input pins input pins for key interrupt based on or condition result of pin inputs. these can be set to key input pins by 1-bit with key inter- rupt control register (keyt3_1imd, key3_2_imd). when not used for key input, these pins can be used as normal i/o pins. key1 48 key2 47 key3 46 key4 45 key5 44 key6 43 key7 42 pins no i/o function description
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e .. for the mmod setup in rewriting the flash memory , refer to [chapter internal flash memory] of lsi user?s manual. .. led0 1 output led drive pins large current output pins. select the large current output by led- cnt registers. when not used for led output, these pins can be used as normal i/o pins. led1 2 led2 3 led3 4 led4 5 led5 6 led6 7 led7 8 dmod 20 input mode switch input pins set always to v dd5 . mmod 10 input rom area switch input pins at start set always to v ss . pins no i/o function description
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.4 block diagram 1.4.1 block diagram figure:1.4.1 block diagram p06 p05 p04 tm0iob,tm2iob,p03 sbt1a,p02 t m8iob,sbo1a,txd1a,p01 tm7iob,sbi1a,rxd1a,p00 irq0, p20 irq1, p21 irq2, p22 irq3, p23 irq4, p24 sbo4b,sda4b,p33 sbt4b,scl4b,p34 sbi4b,p35 sbo0b,txd0b,p43 sbi0b,rxd0b,p44 sbt0b,p45 p46 p47 port 0 port 1 port 5 low-speed oscillator circuit pll osc1, p2 5 osc2, p2 6 xi, p90 xo, p91 rom 128 kb 8-bit timer 0 8-bit timer 1 8-bit timer 2 8-bit timer 3 8-bit timer a time base timer 6 16-bit timer 7 16-bit timer 8 a/d converter key7,d7,p57 key6,d6,p56 key5,d5,p55 nbuzzer,key4,d4,p54 buzzer,key3,d3,p53 SBT0A,key2,d2,p52 sbi0a,rxd0a,key1,d1,p51 s bo0a,txd0a,key0,d0,p50 cpu mn101e ram 6 kb serial interface 0 serial interface 1 serial interface 2 serial interface 4 watchdog timer buzzer external interrupt vdd18 vdd5 vss mmod dmod pb3,an11 pb2,an10 pb1,an9 pb0,an8 pa7,led7,an7 pa6,led6,an6,tm8io a pa5,led5,an5,tm7io a pa4,led4,an4 pa3,led3,an3,tm3io a pa2,led2,an2,tm2io a pa1,led1,an1,tm1io a pa0,led0,an0,tm0io a p95 p94 p93 p92 p87 p86 p85 p84 p83 p82 p81 p80 high-speed oscillator circuit port 6 port 7 port 2 p10 port 3 port 4 sbt4a,scl4a,p67 sbo4a,sda4a,a12,p66 sbi4a,a11,p65 a10,p64 tm3iob,a9,p63 tm1iob,a8,p62 a13,p61 sbt1b,p77 sbi1b,rxd1b,p76 sbo1b,txd1b,p75 p74 p73 sbt2,ncs,p72 sbi2,rxd2,nwe,p71 sbo2,txd2,nre,p70 vref+ port b port a port 9 port 8 nrst, p27
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.5 electrical characteristics when using this lsi, consult our sales offices for the product specifications. structure cmos integrated circuit application general-purpose function cmos 8-bit single chip microcomputer
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.5.1 absolute maximum ratings figure:1.5.1 capacitor connec tion between vdd18 and vss pins a. absolute maximum ratings *2 *3 *4 v ss = 0 v parameter symbol rating unit a1 power supply voltage v dd5 -0.3 to +7.0 v a2 power supply voltage v dd18 -0.3 to +2.5 a3 input pin voltage v i -0.3 to v dd5 +0.3 (upper limit: 7.0 v) a4 output pin voltage v o -0.3 to v dd5 +0.3 (upper limit: 7.0 v) a5 i/o pin voltage v io1 -0.3 to v dd5 +0.3 (upper limit: 7.0 v) a6 peak output current led output i ol1 (peak) 30 ma a7 other than led output i ol2 (peak) 20 a8 all pins i oh (peak) -10 a9 average output current *1 led output i ol1 (avg) 20 a10 other than led output i ol2 (avg) 15 a11 all pins i oh (avg) -5 a12 power dissipation p d 400 mw a13 a14 a15 a16 operating ambient temperature t opr -40 to +85 ? c a17 storage temperature t stg -55 to +125 *1 applied to any 100 ms period. *2 connect at least one bypass capacitor of 0.1 ? f + 1.0 ? f or larger between vdd5 pin and gnd for the internal power voltage stabilization. *3 connect appropriate capacitor about 0.1 ? f + 1.0 ? f between vdd18 pin and vss pin, near the microcontroller according to the figure:1.5.1 shown below for the internal power supply stabilization. *4 the absolute maximum ratings are the limit values beyond which the lsi may be damaged. lsi vdd18 vss 0.1 f 1.0 f
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.5.2 operating conditions b. operating conditions v ss = 0 v ta = -40 ? c to +85 ? c parameter symbol conditions rating unit min typ max power supply voltage *5 b1 power supply voltage v dd1 4.0 5.5 v b2 ram retention power supply voltage v dd2 during stop mode 2.2 5.5 operating speed *6 b3 instruction execution time fs t c1 v dd5 = 4.0 v to 5.5 v (when romhnd flag of handshake reg- ister is ?1?.) 0.05 ? s b4 t c2 v dd5 = 4.0 v to 5.5 v (when romhnd flag of handshake reg- ister is ?0?.) 0.10 b5 t c3 v dd5 = 4.0 v to 5.5 v 61 *5 fs: machine clock frequency *6 tc1 to 2 : when the machine clock is selected from external high-speed oscillation, internal high-speed oscillation, or both t he oscil- lations multiplied by pll. external oscillator 1 figure:1.5.2 b6 frequency f hosc1 v dd5 is within the specif ied operating power supply voltage range. (refer to the ratings of b1 to b2 for the operating supply voltage range) 2.0 10 mhz b7 internal feedback resistor r f10 v dd5 = 5.0 v 980 k ? external oscillator 2 figure:1.5.3 b8 frequency f sosc1 v dd5 = 4.0 v to 5.5 v 32.768 khz b9 internal feedback resistor r f20 v dd5 = 5.0 v 6.2 m ?
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e figure:1.5.2 external oscillator 1 figure:1.5.3 external oscillator 2 .. connect external capacitors suited for the used oscillator. the reference value denotes external capaci ty value based on our matching result. when crystal oscillator or ceramic oscillator is used, the oscillation frequency is changed depending on the value of capacito r. for external capacity value, please consult the oscillator manufacturer and perform matching tests enough for determining appropriate values. .. p25/osc1 r f10 f hosc1 p26/osc2 lsi c 12 c 11 feedback resistor is embedded. p90/xi r f20 f sosc1 p91/xo lsi c 22 c 21 feedback resistor is embedded.
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e v dd5 = 4.0 v to 5.5 v v ss = 0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max external clock input 1 os c1 (osc2 is unconnected) b10 clock frequency f hosc2 210.0 mhz b11 high-level pulse width *7 t wh1 figure:1.5.4 45 ns b12 low-level pulse width *7 t wl1 45 b13 rising time t wr1 figure:1.5.4 05.0 b14 falling time t wf1 05.0 *7 the clock duty ratio should be 45 % to 55 % external clock input 2 xi (xo is unconnected) b15 clock frequency f sosc2 32.768 khz b16 high-level pulse width *7 t wh2 figure:1.5.5 4.5 ? s b17 low-level pulse width *7 t wl2 4.5 ? s b18 rising time t wr2 figure:1.5.5 020 ns b19 falling time t wf2 020 ns
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e figure:1.5.4 osc1 timing chart figure:1.5.5 xi timing chart t wh1 t wl1 0.8v dd5 t wf1 t wr1 0.2v dd5 t wc1 t wh2 t wl2 0.8v dd5 t wf2 t wr2 0.2v dd5 t wc2
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.5.3 dc characteristics c. dc characteristics v ss = 0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max power supply current *8 c1 power supply current during operation i dd1 v dd5 =5 v fosc=10 mhz [double-speed mode: fs=fosc] (pll is not used) *9 514 ma c2 i dd2 v dd5 =5 v fosc=10 mhz [multiplied by 2, divided by 2: fs=fosc] (pll is used) *9 618 c3 i dd3 v dd5 =5 v fosc=10 mhz [multiplied by 2: fs=20 mhz] (pll is used) *9 920 c4 i dd4 v dd5 =5 v frc=16 mhz [double-speed mode: fs=16 mhz] (pll is not used) *9 615 c5 power supply current during operation i dd5 v dd5 =5 v fx=32.768 khz [fs=fx/2] 200 400 ? a c6 power supply current during stop mode i dd6 v dd5 =5 v 145 245 ? a *8 measured without loading (pull-up and pull-down resistors are not connected.) to measure the power supply current during operation i dd1 to i dd4 ; 1. set all i/o pins to input mode, 2. set the cpu mode to ?normal mode?, 3. fix pin mmod to v ss level and input pins to v dd5 level 4. input the rectangular wave of 10 mhz with amplitude of v dd5 and v ss , from pin osc1. to measure the power supply current during slow mode i dd5 ; 1. set all i/o pins to input mode 2. set the cpu mode to "slow mode" 3. fix the mmod to v ss level and input pins to v dd5 level to measure the power supply current during stop mode i dd6 ; 1. set the cpu mode to ?stop mode?, 2. fix pin mmod to v ss level and input pin to v dd5 level 3. open pin osc1. *9 when romhnd flag of handshake register is set to ?1?
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e v dd5 = 4.0 v to 5.5 v v ss = 0 v ta = -40 ? c to +85 ? c parameter symbol conditions rating unit min typ max input pin 1 atrst, mmod c7 input high voltage v ih1 0.8v dd5 v dd5 v c8 input low voltage v il1 0 0.2v dd5 c9 input leakage current i lk1 v in = 0 v to v dd5 2 ? a input pin 2 p27/nrst c10 input high voltage v ih2 0.8v dd5 v dd5 v c11 input low voltage v il2 0 0.15v dd5 c12 pull-up resistor r rh2 v dd5 =5 v, v in = v ss 10 50 100 k ? i/o pin 3 p00 to p06, p10, p20 to p26, p62 to p67, p70 to p77, p80 to p87 c13 input high voltage v ih3 0.8v dd5 v dd5 v c14 input low voltage v il3 0 0.2v dd5 c15 input leakage current i lk3 v in =0 v to v dd5 2 ? a c16 pull-up resistor r rh3 v dd5 =5.0 v, v in =v ss pull-up resistor on 10 50 100 k ? c17 output high voltage v oh3 v dd5 =5.0 v, i oh =-0.5 ma 4.5 v c18 output low voltage v ol3 v dd5 =5.0 v, i ol =1.0 ma 0.5 i/o pin 4 pa0 to pa7 c19 input high voltage v ih4 0.8v dd5 v dd5 v c20 input low voltage v il4 0 0.2v dd5 c21 input leakage current i lk4 v in =0 v to v dd5 2 ? a c22 pull-up resistor r rh4 v dd5 =5.0 v, v in =v ss pull-up resistor on 10 50 100 k ? c23 output high voltage v oh4 v dd5 =5.0 v, i oh =-0.5 ma 4.5 v c24 output low voltage 1 v ol41 v dd5 =5.0 v, i ol =1.0 ma led output off 0.5 c25 output low voltage 2 v ol42 v dd5 =5.0 v, iol=15.0 ma led output on 1.0
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e v dd5 = 4.0 v to 5.5 v v ss = 0 v ta = -40 ? c to +85 ? c parameter symbol conditions rating unit min typ max input pin 5 p50 to p57, p90, p91, p94 c26 input high voltage v ih5 0.8v dd5 v dd5 v c27 input low voltage v il5 0 0.2v dd5 c28 input leakage current i lk5 v in =0 v to v dd5 2 ? a c29 pull-up resistor r rh5 v dd5 =5.0 v, v in =v ss pull-up resistor on 10 50 100 k ? c30 pull-down resistor r rl5 v dd5 =5.0 v, v in =v dd5 pull-down resistor on 10 50 100 c31 output high voltage v oh5 v dd5 =5.0 v, i oh =-0.5 ma 4.5 v c32 output low voltage v ol5 v dd5 =5.0 v, i ol =1.0 ma 0.5 input pin 6 dmod c33 input high voltage v ih6 0.8v dd5 v dd5 v c34 input low voltage v il6 0 0.2v dd5 c35 pull-up resistor r rh6 v dd5 =5.0 v, v in =v ss pull-up resistor on 10 50 100 k ?
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.5.4 a/d converter characteristics .. even if a/d function is not us ed, the voltage of vref+ pin must be set between 4.0 v and v dd5 . .. d. a/d converter characteristics *10 v dd5 = 5.0 v v ss = 0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max d1 resolution 10 bits d2 non-linearity error 1 v dd5 =5.0 v, v ss =0 v v ref+ =5.0 v t ad =800 ns 3 lsb d3 differential non-linear- ity error 1 3 d4 zero transition voltage v dd5 =5.0 v, v ss =0 v v ref+ =5.0 v t ad =800 ns 10 30 mv d5 full-scale transition voltage 4970 4990 d6 a/d conversion time t ad =800 ns 12.93 ? s d7 sampling time t ad =800 ns 1.6 d8 reference voltage v ref+ note) 4.0 v dd5 v d9 analog input voltage v ss v ref+ d10 analog input leakage current channel off v adin =v ss to v dd5 2 ? a d11 reference voltage pin input leakage current ladder resistance off v ss ? v ref+ ? v dd5 5 d12 ladder resistance r ladd v dd5 =5.0 v 15 40 80 k ? *11 t ad is a/d conversion clock cycle. the specification values of d2 to d5 are guaranteed on the condition of v dd5 =v ref+ =5 v, v ss =0 v.
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.5.5 auto reset characteristics 1.5.6 internal high-spee d oscillation circuit e. auto reset characteristics v dd5 = v rst to 5.5 v v ss = 0 v ta = -40 ? c to +85 ? c parameter symbol conditions rating unit min typ max power supply voltage e1 operating supply voltage v dd7 auto reset is used v rst 5.5 v power supply voltage e2 power detection level v rst1 at rising 4.10 4.30 4.50 v e3 power detection level v rst2 at falling 4.00 4.20 4.40 e4 supply voltage change rate ? t/ ? v2ms/v f. internal high-speed oscillation circuit v dd5 = 4.0 v to 5.5 v v ss = 0 v parameter symbol conditions rating unit min typ max f1 internal high-speed oscil- lation circuit frequency f rc ta = - 4 0 ? c to +85 ? c16mhz f2 temperature dependence of oscillation frequency f rc3 ta = 2 5 ? c -5.0 5.0 % f3 f rc4 ta = - 4 0 ? c to +85 ? c
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.5.7 flash eeprom program conditions g. flash eeprom program conditions v dd5 = 4.0 v to 5.5 v v ss = 0 v*11 ta = -40 ? c to +85 ? c parameter symbol conditions rating unit min typ max g1 programming supply volt- age v ddew 4.0 5.5 v g2 programming/erasing times of 32kb, 20kb sector *2 e max1 1000 times g3 programming/erasing times of 4kb sector *2 e max2 10000 times g4 data retention period of 32kb, 20kb sector *1 t hold1 ta = 8 5 ? c, p/e times ?? 1000 20 years g5 data retention period of 4kb sector *1 t hold2 ta = 8 5 ? c, p/e times ?? 1000 *2 20 years t hold3 ta = 6 5 ? c, p/e times ?? 10000 *2 20 years *1 contain the period when power supply voltage is not supplied. *2 programming/erasing times(p/e times) is counted by the number of time a sector is erased. it is controlled on sector basis. for example, if writing 1 byte of data in any sector for hundred of times and then erasing the sector, a single rewriting is co unted. also, the number of times of rewriting in another sector, in which erasing is not performed, is not counted. overwriting data is disabled. to rewrite data, write the data after erasing sectors.
mn101ef93g 8-bit single-chip microcontroller publication date: february 2015 pubno. 21693-013e 1.6 package dimension ? package code: lqfp080-p-1414eunit: mm figure:1.6.1 80-pin lqfp package dimension .. this package dimension is subject to change. before using this product, please obtain prod- uct specifications from our sales offices. ..
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